The present invention relates to the field of electroless deposition, in particular to a method for electroless formation of phosphorus-containing metal films, such as cobalt-tungsten-phosphorus (hereinafter referred to as Coxe2x80x94Wxe2x80x94P) system films on copper substrates with Pd-free activation. Such coatings may find application in semiconductor manufacturing where properties of deposited films and controllability of the composition and of physical and chemical characteristics of the deposited films may be critically important. More particularly, the present invention may find application in processes for fabricating semiconductor devices using a trench wiring technique, such as damascene processes, or the like.
Electroless deposition is a process for depositing a thin layer or layers of a material or materials onto a substrate, which normally consists of immersing the substrate in a deposition bath that contains ions of the material to be deposited, whereby some of these ions precipitate onto the surface of the substrate. In contrast to electroplating processes, the electroless deposition process does not need an externally applied electric field to facilitate the deposition process. An advantage of an electroless deposition process is that it can be selective, i.e., the material can be deposited only onto areas that demonstrate appropriate electrochemical properties. Therefore, local deposition can be performed more effectively onto metals that exhibit an affinity to the material being deposited or onto areas pretreated or pre-activated, e.g., with a catalyst. The material or catalyst applied prior to deposition onto the selected areas is sometimes called a xe2x80x9cseed materialxe2x80x9d or xe2x80x9cseed layerxe2x80x9d and the ratio of the deposition rate on the activated regions to the deposition rate at the non-activated regions is known as the xe2x80x9cdeposition process selectivityxe2x80x9d. It is understood that the deposition rate may also depend on such characteristics of the activated areas, as dimensions, profiles of the exposed surfaces, and distances between the portions of the areas to be activated. For many applications, it is very important to provide deposition of uniform thickness. Other important characteristics of the electroless deposition are selectivity of the process and adherence of the deposited layer to the substrate.
Electroless deposition of various metals from deposition solutions onto catalytically pretreated surfaces has been widely used in the past in the printed circuit board industry for the production of wiring layers and interlayer connections. Later, a similar technique was transfered to semiconductor industry for the production of metal interconnects in semiconductor (IC) chips. The electroless deposition technique is advantageous to other known metal deposition techniques such as different types of sputtering and evaporations. One advantage is the use of less expensive equipment. Another advantage is selectivity and controllability of the process. For example, deposition can be performed only onto pretreated areas. As a result, it becomes possible to reduce the number of lithographic and etching steps, which are the most expensive stages of the semiconductor manufacture. Another advantage is that electroless deposition well matches the present trend for using copper as interconnect materials instead of aluminum, suicides, or the like. It is well known that the new generations of LSI are associated with the use of copper, which possesses very high electrical conductivity. The problem encountered by traditional techniques (that include anisotropic etching) in transfer to copper is that copper is difficult to etch anisotropically. Yet another advantage of electroless deposition is that it to a lesser degree depends on such features of the substrate surface as angles or depth of trenches and vias, etc. This property enables deposition into deep via holes on substrates that could not be uniformly covered by sputtering and evaporation.
Many surface activation techniques that precede electroless deposition are known in the art. The most common applications of electroless deposition to integrated circuit manufacturing comprise deposition of nickel, cobalt, palladium, or copper onto one of two types of substrate surfaces. The first type of substrate surface comprises conductive regions of substrates that are generally formed of silicon, aluminum, or aluminum alloys. The second type of substrate comprises a non-conductor such as silicon dioxide or a polymeric insulator. The reported surface activation techniques applied to these substrates usually fall into one of four categories: (1) catalyst film deposition by evaporation or sputtering, (2) catalyst film deposition by electrochemical or chemical surface modification, and (3) catalytic film deposition from a colloidal suspension; (4) photon-enhanced activation by laser or wide spectrum irradiation.
Metals of Group VIII (e.g., palladium and platinum) are frequently used as catalytic surface activators in electroless deposition methods. Catalytic films of palladium or platinum for subsequent electroless deposition can be readily deposited by evaporation or sputtering techniques. The films deposited with these techniques can be patterned by well-known lithographic techniques, e.g., subtractive etching or liftoff. Large features and/or dense patterns of small features are relatively easy to plate with this method.
It has been found out that in electroless deposition, palladium activation from an aqueous solution demonstrates higher catalytic activity of films than of palladium films deposited by sputtering or evaporation (see U.S. Pat. No. 6,180,523 issued in 2001 to Chwan-Ying Lee, et al.). The reduced catalytic activity results in the formation of a less uniform films. Furthermore, it becomes more difficult to deposit a film on small and isolated features such as metallization patterns on semiconductor devices.
There are known various methods suitable for improving catalytic activity of the surface with the use of palladium prior to electroless deposition.
As has been mentioned above, copper is not easily dry-etched. Therefore, in the formation of a copper wiring, a process of forming a trench wiring is promising. The trench wiring is produced by a process in which a predetermined trench is preliminarily formed in an interlayer dielectric comprised of, for example, silicon oxide, and the trench is plugged with a wiring material. Then, the excess wiring material is removed by, for example, a chemical mechanical polishing (hereinafter, frequently referred to simply as xe2x80x9cCMPxe2x80x9d) process, to thereby form a wiring in the trench.
The copper wiring is generally used in the form of a multilayer wiring. When such a multilayer copper wiring is formed, no barrier film, which prevents copper from diffusing, is present on the surface of the copper wiring. Therefore, before an upper layer wiring is formed on the copper wiring, as a diffusion-preventing film for copper, a barrier film comprised of silicon nitride, carbon nitride or the like is formed on the copper wiring. Silicon nitride, silicon carbide, and silicon oxynitride have relative dielectric constants larger than that of silicon oxide. Therefore, it is considered that these are advantageous in a method in which the surface of copper after the CMP process is selectively coated with these. In addition, U.S. Pat. No. 5,695,810 issued to V. Dubin, et al. on Dec. 9, 1997 discloses a method in which the surface of copper is coated with a cobalt tungsten phosphorus (Coxe2x80x94Wxe2x80x94P) film. In this method, cobalt tungsten phosphorus is deposited by an electroless plating method using the surface of copper as a catalyst.
A disadvantage of the above method is that it offers deposition of a Coxe2x80x94Wxe2x80x94P barrier layer onto copper using copper as a catalyst without additional activation. Such a process is characterized by a low deposition rate, which could be improved with the use of catalytic activation.
Further, Japanese Patent Application Laid-Open Specification No. 9-307234 filed by Yo. Funada, et al., on May 20, 1996 (which is one of basic applications of U.S. Pat. No. 5,830,563) discloses a method used in a printed-wiring substrate, in which the exposed copper surface is subjected to palladium displacement plating, and electroless plating is conducted using the displaced palladium as a catalyst nucleus. On the other hand, as a catalyst activation treatment for electroless plating, a method in which palladium ions are reduced utilizing an oxidation reaction of tin ions, a method using a palladium sol, a method using a silane coupling agent, and the like are known.
However, the catalytic activity of copper to oxidize a reducing agent is lower than that of gold (Au), nickel (Ni), palladium (Pd), cobalt (Co), or platinum (Pt). Therefore, in the electroless plating method using a hypophosphite as a reducing agent, when a metal having an ionization potental larger than that of copper is electroless-plated on copper, a unfavorable phenomenon such that plating cannot be conducted at all, the plating cannot be conducted uniformly, the plating rate is low, or the like is likely to occur.
In addition, in the palladium catalyst method used in a general electroless plating, it is known that palladium is present in an island form on the entire surface of both a copper wiring and in many cases on an interlayer dielectric film. In this case, a barrier layer comprised of cobalt tungsten phosphorus is formed by deposition using, as a catalyst nucleus, the palladium formed in an island form on the entire surface of copper wiring and, in many cases, on the surfaces of interlayer dielectric films, especially on those formed by high carbon content materials. However, typically palladium is present as a plurality of separate nucleation sites, especially on the surface of polycrystalline materials, such as copper. Therefore, the barrier layer, which grows using such palladium as a nucleus, is likely to be also a non-uniform film. In addition, for forming the barrier layer as a continuous film on the entire surface of both the copper wiring and the interlayer dielectric film, it is necessary to increase the thickness of the barrier layer, and the thickness depends on the density of the palladium formed in an island form. Such problems make it difficult to control the process.
Further, in the aforementioned known palladium catalyst methods, it is difficult to selectively form a palladium catalyst layer on the copper wiring, and thus, palladium elements disadvantageously adsorb onto the entire surface to be treated. In addition, in the palladium catalyst method using tin ions, it is confirmed that tin elements are drawn into the palladium layer, and problems are encountered in that tin causes the wiring resistance to rise and the long-term reliability of the wiring to be poor.
Attempt has been made to solve the above problems by a method disclosed in U.S. Pat. No. 6,479,384 issued on Nov. 12, 2002 to Naoki Komal, et al. This patent describes a process for fabricating a semiconductor device by forming on a copper wiring a barrier layer, which functions as a diffusion-preventing film. A catalytic metal film, which serves as a catalyst in the electroless plating method, is selectively formed on the copper wiring by a displacement deposition method using a displacement deposition solution at a temperature about 30xc2x0 C., and the barrier film is selectively formed on the catalytic metal film by electroless plating. The purpose of the aforementioned invention is to selectively and uniformly carry out the catalytic activation on the surface of the metal wiring made of copper or a copper alloy by using palladium so as to improve reliability of the wiring and plating property of the electroless plating method using a hypophosphite as a reducing agent. More particularly, the aforementioned process is intended for fabricating a semiconductor device using a trench wiring technique, such as a dual Damascene process or a single Damascene process.
U.S. Pat. No. 6,486,055 issued in 2002 to Chan-Hwa Jung, et al. discloses a method for forming copper interconnections in semiconductor component using electroless plating system, which enables copper to be grown only in corresponding interconnection regions. In such a method, a wafer is cleaned and pretreated with a palladium seed solution so as to cause spontaneous catalytic activation, and simultaneously the process temperature is varied to grow metal seed particles from the metal seed pretreating solution. The wafer is cleaned to remove the metal seed from the wafer surface, and the wafer is finally plated with an electroless plating bath to grow copper in the metal seed formed regions. This method simplifies the processes and reduces process costs by substituting a wet process for the existing vacuum pretreating process. Also, a wafer planarization process can be omitted by selectively growing copper only in desired interconnections. Compared with the existing ultraviolet radiation photolithography process, the selective copper growth process of the method has an advantage of relative simplicity.
In all methods described above the catalytic activation of the surface to be treated is based on the use of palladium. However, activation of semiconductor substrate surfaces with palladium has a number of disadvantages which are the following: 1) palladium is a very expensive material and therefore the use of palladium makes the entire process expensive; 2) palladium is not a readily available material and in commercial quantities is available only from one country; 3) palladium activation is carried out by deposition of palladium; however, at the initial stage of deposition palladium precipitates in the form of islands, which are growing simultaneously in three directions with noncontrollable growth; this results in the formation of rough surfaces on the subsequent stages of deposition; 4) since palladium possesses low selectivity, it may be easily absorbed by the polymeric surface (low-K polymers) that may surround the copper area onto which palladium is precipitated.
U.S. Pat. No. 4,002,778 issued in 1977 to H. Bellis et al. describes a process of electroless deposition of nickel or cobalt onto conductive substrates without the use of palladium as a seed layer. However, the solution offered by the authors contains salts of alkali-metal salts, which are extremely undesirable for use in semiconductror devices.
It is an object of the present invention to provide a method for selective deposition of Coxe2x80x94Wxe2x80x94P system films onto copper with palladium-free activation. It is another object to provide the aforementioned method in which efficiency of selective deposition of a Coxe2x80x94Wxe2x80x94P system films is achieved by forming a hydrogen-rich aquacomplexes on the metal surface prior to deposition. Another object is to provide the aforementioned method as simple and inexpensive. Still another object is to provide the aforementioned method, which excludes an additional step of palladium deposition.
The method for selective deposition of Coxe2x80x94Wxe2x80x94P system films onto copper with palladium-free activation consists of creating hydrogen-rich complexes on the metal surface prior to deposition. More specifically, the method consists of creating the aforementioned complexes on the copper surfaces prior to electroless deposition of a Coxe2x80x94Wxe2x80x94P system films. This is achieved by contacting the copper surface with reducing agents for a short period of time and at an elevated temperature. Such reducing agents comprise a hypophosphorous-acid-based or borane-based reducing agents such as dimethylamine borane. Hypophosphorous acid is preferred since it is more compatible with the electroless deposition solution.